Agile STL development and HW Mechanisms for their Efficient Execution
PR FESR 2021-2027 OP1 OS1 Azione 1.1.4 ”Ricerca e sviluppo per le imprese anche in raggruppamento con organismi di ricerca”
Bando n.2 “Progetti di ricerca e sviluppo per le MPMI e Midcap”
CUPST: 27717.29122023.043000398_2127
The continuous evolution of integrated circuit technologies and artificial intelligence algorithms has enabled the development of increasingly complex and intelligent processing systems. These advances have resulted in smaller, more powerful, and energy-efficient devices, generating wide interest across industries and research sectors — including safety-critical systems, where reliability and correct operation under all circumstances are essential.
In safety-critical domains such as automotive, aerospace, and industrial automation, systems must comply with strict standards that require protection mechanisms against hardware faults caused by environmental factors, voltage fluctuations, aging, or wear. One widely adopted solution for ensuring fault detection and system reliability is the use of Software Test Libraries (STL) — self-test routines that periodically verify the correct operation of a device’s internal hardware components.
STLs offer a crucial advantage: being purely software-based, they can be implemented even on off-the-shelf devices whose hardware design is already fixed. This makes them a flexible and cost-effective alternative to hardware redundancy, which in complex processors significantly increases cost, power consumption, and silicon area. For this reason, STLs have become essential protection mechanisms in many safety-critical applications, particularly within the automotive industry.
However, their execution introduces runtime overhead. Since STLs consume CPU resources, they can impact performance and increase execution time, especially in systems where hardware modifications are no longer possible. In contrast, processors that still allow small design adjustments present an opportunity to mitigate this overhead — which is one of the central goals of the project proposed by Resiltech.
Resiltech is internationally recognized for its expertise in developing STLs for both microcontrollers (MCU) and processors (MPU) and collaborates with numerous CPU and SoC manufacturers. To maintain its leadership, the company aims to enhance the efficiency and diagnostic effectiveness of its libraries. The primary challenge is to achieve high diagnostic coverage without excessively burdening system performance — a task that becomes increasingly difficult as processor architectures grow more complex.
Modern CPUs, particularly those at the application level, include multiple advanced architectural features — such as multi-line pipelines and out-of-order execution — which make it difficult to predict how software interacts with hardware components. This unpredictability complicates the design of effective test routines capable of achieving the diagnostic coverage required by safety standards. The situation is further aggravated by hierarchical memory structures and cache behavior, where cache misses introduce additional execution time variability, affecting both application and diagnostic software.
To address these issues, the project proposes the development of a dedicated hardware component designed to optimize STL execution. This module would use a dedicated memory for STL code and data, allowing the test routines to bypass the regular memory subsystem and thus avoid cache-related slowdowns. By doing so, it would reduce execution time, improve timing predictability, and lower overall system overhead. Furthermore, the hardware unit could monitor the CPU’s operational state to detect idle periods and opportunistically execute portions of the STL during those times, further minimizing the impact on runtime performance.
The project will define the requirements, architecture, and implementation of this configurable and reusable hardware IP core, to be integrated into a reference processor within the RISC-V ecosystem. RISC-V was chosen due to its open and rapidly evolving nature, as well as existing collaborations between Resiltech and RISC-V partners in the automotive domain. The resulting solution is expected to reduce STL execution time and energy consumption, while expanding Resiltech’s portfolio and reinforcing its competitive position in the market.
A second objective of the project concerns improving the STL development process itself. Due to the high complexity of modern CPUs, developing effective STLs requires an iterative process involving Verification and Validation (V&V) through fault simulation campaigns. These simulations assess diagnostic coverage and guide the refinement of test routines by identifying hardware modules that are insufficiently protected.
Resiltech’s current process already includes these stages, but the increasing heterogeneity of hardware description languages (HDLs) and design tools has highlighted opportunities for optimization. The company aims to enhance process efficiency by automating CPU structural reconstruction and organizing fault simulation results within a language-agnostic database. This database will allow engineers to query CPU regions with inadequate coverage quickly, simplifying analysis and reducing development time. Overall, the project’s outcomes will strengthen Resiltech’s technological leadership by delivering faster, more energy-efficient STL mechanisms and a streamlined development process, ultimately enabling safer and more reliable next-generation processing systems.
