ASSURING SAFETY OF HW PLATFORMS IN CRITICAL TRANSPORT APPLICATION
Piano Nazionale di Ripresa e Resilienza (PNRR) – MISSIONE 4 COMPONENTE 2
CUP I87H24000590008
With the evolution of control systems in transportation—such as next-generation automated railway interlocking systems and Advanced Driver Assistance Systems (ADAS) for vehicle guidance—hardware processing units (MCU, CPU, GPU, DSP, etc.) have become critical components of these real-time software systems. Although modern manufacturing processes have significantly improved the quality of these components, faults or malfunctions can still occur during operation due to component degradation caused by external factors or aging. If not detected in time, such failures can propagate and lead to catastrophic system-wide failures.
Current industrial fault detection strategies rely on both hardware-based (e.g., ECC, LBIST, lock-step, etc.) and software-based (e.g., self-test libraries) safety mechanisms, which are built on well-defined hardware fault models. The effectiveness of any detection mechanism strictly depends on the fault model it is based on and its fidelity in representing the actual failure behavior of the monitored components.
The fault model most commonly used in state-of-the-art approaches is the “stuck-at” model at the logic gate level. However, as highlighted by numerous scientific studies—for example, [E. J. McCluskey and Chao-Wen Tseng, “Stuck-fault tests vs. actual defects,”] and [Chhabria, Vidya A., and Sachin S. Sapatnekar. “Impact of self-heating on performance and reliability in FinFET and GAAFET designs.”]—this model does not accurately reflect the real fault phenomena occurring in the materials involved. These works instead propose the path delay fault model as a more accurate alternative.
The stuck-at model represents a significant limitation, as it hinders the effective design and accurate assessment of safety mechanisms developed under such a fault model.
This project therefore aims to introduce a significant process innovation in the development and evaluation of safety mechanisms for digital processing systems. It will do so by studying fault phenomena based on the path delay model and defining a methodology for the management and characterization of these faults. The successful achievement of this challenging goal will be demonstrated through the ad hoc development of a new self-test library, used as a case study. Its performance will be measured through a comprehensive fault injection campaign on a target microprocessor.
The development of this project is expected to involve ARTES 4.0, leveraging the following expertise:
- Understanding of degradation phenomena in next-generation digital circuits (e.g., FinFET), and the definition of an accurate fault model based on path delays.
- Derivation of probabilistic failure models and corresponding strategies for sampling critical events.
