SAFETY OF RISC-V HW PLATFORMS IN AUTOMOTIVE APPLICATIONS
CUP I 83D24000110005
BANDO MEDITECH N.3 – 2023
PIANO NAZIONALE DI RIPRESA E RESILIENZA (PNRR) – MISSIONE 4 COMPONENTE 2 “Dalla ricerca all’impresa” INVESTIMENTO 2.3 “Potenziamento ed estensione tematica e territoriale dei centri di trasferimento tecnologico per segmenti di industria”
With the evolution in the automotive domain of Software Defined Vehicles (SDV), driving support ADAS systems, and the use of AI-based technologies such as Collision Avoidance, Night Vision, Blind Spot Detection or Adaptive Braking, HW processing units (CPU, GPU, DSP… ), have become critical components. In addition, this strong growth in modern vehicles of features increasingly based on software implementations has generated an increase in the supply of components intended for this market, particularly for safety critical applications, where adherence to the ISO26262:2018 safety standard requires the use of fault detection measures in proportion to the degree of criticality of the component.
While modern manufacturing processes have greatly increased the quality of these hardware components, it is inevitable that failures or malfunctions will occur during operation due to degradation of the components by external factors or their aging. Such malfunctions, if not detected in a timely manner, can propagate to the point of catastrophic failure of the entire system. Current industrial fault detection strategies for the automotive market consist of HW (ECC, LBIST, lock-step, watchdog, etc.) and SW (self-test libraries) safety mechanisms. These technologies are essential for a variety of embedded devices that also extend to System on Chip (SoC) used to support AI, which always integrate a number of embedded host CPUs to control HW components that accelerate AI algorithms, and such CPUs need proper SW test libraries.
While CPU manufacturers already firmly engaged in supplying components for safety critical markets (i.e., ARM, Intel) already integrate solutions for early HW failure detection, which are based on the proprietary architectures they have developed, a substantial and growing number of companies in the process of entering these markets are looking for solutions for software self-testing of their architectures, the absence of which is often a significant technological barrier to market entry. A large part of this new market is based on RISC-V HW architectures, for which no such fault detection mechanisms yet exist in the state of the art.
The effectiveness of a detection mechanism depends both on the development process and knowledge of processor specifics and on the fidelity of the failure model to the actual failure mode of the monitored components. This project therefore aims to (i) define the processes required for the development of self-test libraries for new CPUs based on RISC-V architectures, (ii) design and implement the tools to support library design, verification, and validation (iii) define and apply HW failure models more representative of those commonly used in industrial processes (i.e. stuck-at), typical of more advanced manufacturing processes (e.g., finfet on process nodes smaller than 28nm), such as path delay, iv) design and implement for demonstration purposes a self-test library for a RiscV application core using the results obtained in this project, v) study of methodologies and tools for distribution, market access, and IPR management of self-test libraries.
Starting from several proofs of concept developed internally by Resiltech, covering the various technologies needed in all phases of development verification and validation of an STL, the goal of this project is to reach a TRL 7 grade, so that a methodology ready to be used in Resiltech for the production and commercialization of Self Test libraries for RISC-V processors for the automotive market will be available. In order to achieve the above objective in (v), the involvement of CC MEDITECH is expected, which will provide access to the digital and FIWARE platform and make experts available to create together with Resiltech a multidisciplinary team to support the project.
In conclusion, this project aims to bring a major process innovation in the development and evaluation of security mechanisms for digital processing systems by studying and defining the appropriate design strategy for STL to be used for processing units developed with advanced technologies applied to RISC-V architectures. The effective achievement of this challenging goal will see the development of a new self-test library for RISC-V application cores whose performance will be measured through a fault injection campaign implemented on an appropriate digital test bench. The business model will be supported by IPR deployment and control tools through the involvement of the MEDITECH consortium.
