Required qualification:
Master's Degree in Electronic Engineering (5 years)

Required experience:

• more than 7 years in the sector of the design and/or the verification and/or the analysis of digital architectures
• knowledge of the digital architectures of System on Chip based on programmable cores

Desired experience:

• experience in the FMEDA analysis.
• experience on RISK multicore architectures based on ARM and MIPS and on its programming.
• Knowledge of the base cases in the automotive and industrial environment of the Functional Safety.

Main tasks:

• FMEDA analysis of complex SoC based on programmable cores.
• Specifications definition for the products development: HW IP and firmware for Functional Safety applications.
• Management of RTL simulations and gate level of complex Systems on Chip for fault injection based on the Synopysis toolchain (work team composed of 4-5 members)
• Management of the relationships with the customers.

Availability:
Immediate, but the integration during the 2019 is took into consideration

Location:
Pontedera.

Business trips:
Possibility of national and internation business trips for meetings with the customers (on the average, no more than one business trip per month).