JUNIOR SAFETY AND VERIFICATION & VALIDATION ENGINEER – TRANSPORTATION

23rd February 2016


Position:
Tempo indeterminato - Full-time


Sector:
V&V&S – Verification and Validation and Safety analysis R&D: Safety Critical System Architect & General Studies


Job Objective:
The candidate will work for the V&V&S (Verification and Validation and Safety analysis) projects, where the safety of people and environment is a key element of the project. The candidate at Resiltech will support in Safety Analysis and Verification and Validation activities along the Resiltech customers systems/products lifecycle in order to get the final system approval by the customer, the ISA (Independent Safety Assessor) and in general any Safety Authority in charge of the solution safety approval. Moreover the candidate will potentially be involved in R&D activities at Resiltech where innovative technologies and cost effective methodologies are developed within the context of Regional, National and European co-founded Projects.


Key Responsibilities:
He/She will:

  • support the team in technical safety and RAM activities: identifying and analyzing the RAMS requirements (Contractual and System Requirements), defining the safety strategy, allocating the RAMS requirements to the subsystem components, assuring their implementation in the solutions, and interfacing the Relevant Safety Authority for the project;
  • support the team in safety analysis (FMEDA) on microcontroller architectures;
  • support the team in developing and verifying diagnostic software;
  • support the team in performing verification activities: documental verifications wrt reference standards;
  • support the team in performing validation activities: execution of testing, both in laboratory and on-field;
  • support the team in performing hazard analysis and in hazard log management, including consolidation of hazards, traceability to requirements, design, verification and validation evidence;
  • participate to Program/Project Meetings (internal and external: with the Customer, Resiltech customers and other entities) when scheduled and/or requested;
  • enforce the proposed evidence of safety and RAM with reference to different standards, if needed, as CENELEC 501xx and ISO 26262;
  • give evidence of the fulfillment of the Norms requirements in relation to the V&V activities


Skills, Experience and Qualifications needed:

  • Master (Laurea Magistrale or equivalent) in Electronic Engineering, Telecommunication Engineering, Computer Science Engineering or Computer Science.
  • Age: Preferred < 30 years
  • Fluency in Italian and English


Skills, Experience and Qualifications that will be acquired with the work in ResilTech:

  • Experience in the safety assurance of systems in projects for Italian Railways market
  • Knowledge of Applicable Norms and Regulations for Italian Railway environment and in general for the international metro and tramway environment (CENELEC, STI, IEC), and in automotive ISO 26262
  • Ability to build manage effectively the relationship with Customers
  • Experience in safety assurance of system/solutions in international environment
  • Knowledge of RAMS analysis methodologies, related Norms and tools;
  • Safety Techniques: Functional Analysis, FMECA, SCIL, DRACAS, PHA, SHA, SSHA, IHA, O&SHA, Hazard Log, Safety Case, HAZOP;
  • RAM Techniques: Development of RAM Analysis, FMECA, FTA/RBD, MTBF, Preventive and Corrective Maintenance Analysis, MTTR, Availability Analysis, Spare Parts Analysis, LCC Analysis);
  • Signalling systems and ATP/ATC systems;
  • RAMS documentation and Lifecycle according to CENELEC 50126;
  • Risk evaluation, Safety Management and SIL apportionment according CENELEC 50129;
  • Methodologies for SW Verification and Validation according to CENELEC 50128.
  • 32 bits RISC Microcontroller architectures for industrial/automotive control application
  • Experience/knowledge in microcontroller embedded programming


SAFETY AND VERIFICATION & VALIDATION ENGINEER – TRANSPORTATION

23rd February 2016


Position:
Tempo indeterminato - Full-time


Sector:
V&V&S - Verification and Validation and Safety analysis R&D: Safety Critical System Architect & General Studies


Job Objective:
The candidate will work for the V&V&S (Verification and Validation and Safety analysis) projects, where the safety of people and environment is a key element of the project. The candidate at Resiltech will manage Safety Analysis and Verification and Validation activities along the Resiltech customers systems/products lifecycle in order to get the final system approval by the customer, the ISA (Independent Safety Assessor) and in general any Safety Authority in charge of the solution safety approval. Moreover the candidate will be involved in R&D activities at Resiltech where innovative technologies and cost effective methodologies are developed within the context of Regional, National and European co-founded Projects.


Key Responsibilities:
He/She will:

  • support the team in technical safety and RAM activities: identifying and analyzing the RAMS requirements (Contractual and System Requirements), defining the safety strategy, allocating the RAMS requirements to the subsystem components, assuring their implementation in the solutions, and interfacing the Relevant Safety Authority for the project.
  • support the team in safety analysis (FMEDA) on microcontroller architectures.
  • support the team in developing and verifying diagnostic software.
  • understand the basic safety concepts and safety design principles (checked-redundant, diversity, fail-safe, safety integrity, common mode and common cause failures, etc).
  • ensure SIL requirements and RAM requirements and their allocation to subsystems/components, providing the risk analysis if necessary;
  • provide hazard log management, including consolidation of hazards, traceability to requirements, design, verification and validation evidence;
  • define in the Safety Plan and RAM plan the technical activities to be performed during the project, and propose the relevant organization according to the CENELEC standards;
  • participate to Program/Project Meetings (internal and external: with the Customer, Resiltech customers and other entities) when scheduled and/or requested;
  • give evidence that the solution meets the defined RAMS requirements from a quantitative and a qualitative point of view;
  • enforce the proposed evidence of safety and RAM with reference to different standards, if needed, as CENELEC 501xx and ISO 26262.
  • give evidence of the fulfillment of the Norms requirements in relation to the V&V activities;
  • support the Project Manager in preparing the RAMS delivery;
  • demonstrate that the solution fulfils the required targets for Reliability Availability and Maintainability;
  • define main criteria for the safety acceptance of the solution.


Skills, Experience and Qualifications needed:

  • Master (Laurea Magistrale or equivalent) in Electronic Engineering, Telecommunication Engineering, Computer Science Engineering or Computer Science.
  • Preferred PhD in Electronic Engineering, Telecommunication Engineering, Computer Science Engineering or Computer Science.
  • Fluency in Italian and English
  • Preferable Age < 35
  • Preferable able to build manage effectively the relationship with Customers
  • Preferable Experience in safety assurance of system/solutions in international environment
  • Knowledge of RAMS analysis methodologies, related standards (ISO26262, CENELEC 5012x) and tools, for example:
    • Safety Techniques: Functional Analysis, FMECA, SCIL, DRACAS, PHA, SHA, SSHA, IHA, O&SHA, Hazard Log, Safety Case, HAZOP;
    • RAM Techniques: Development of RAM Analysis, FMECA, FTA/RBD, MTBF, Preventive and Corrective Maintenance Analysis, MTTR, Availability Analysis, Spare Parts Analysis, LCC Analysis);
    • RAMS documentation and Lifecycle according to CENELEC 50126;
    • Risk evaluation, Safety Management and SIL apportionment according CENELEC 50129;
    • Methodologies for SW Verification and Validation according to CENELEC 50128.
    • 32 bits RISC Microcontroller architectures for industrial/automotive control application
    • Experience/knowledge in microcontroller embedded programming


RECENTLY GRADUATED ELECTRONIC ENGINEER

10th March 2017


Required qualification:
Master's Degree in Electronic Engineering (5 years)


Required experience:
Nothing


Desired experience:
Studies addressed to microelectronics, preferably in the digital environment.


Main tasks:

  • RTL and gate level digital simulations of complex Systems on Chip for the fault injection based on the Synopysis toolchain.
  • Firmware development for ARM and MIPS multicore architectures on microcontroller based systems.


Availability:
Immediate, but the integration during the 2017 is took into consideration


Location:
Pontedera.


Business trips:
Low chance of short national and international business trips.


JUNIOR ELECTRONIC ENGINEER

10th March 2017


Required qualification:
Master's Degree in Electronic Engineering (5 years)


Required experience:
3 to 5 years in the sector of the design and/or the verification and/or the analysis of digital architectures


Desired experience:
Knowledge of digital architectures of System on Chip based on programmable cores. Experience in the FMEDA analysis.


Main tasks:

  • RTL and gate level digital simulation of complex Systems of Chip for fault injection based on the Synopysis toolchain.
  • Management of the firmware development for ARM and MIPS multicore architectures on microcontroller based systems (work team with 2-3 members).
  • FMEDA analysis of HW architectures for indipendent/assisted driving automotive systems.


Availability:
Immediate, but the integration during the 2017 is took into consideration


Location:
Pontedera.


Business trips:
Low chance of short national and international business trips.


SENIOR ELECTRONIC ENGINEER

10th March 2017


Required qualification:
Master's Degree in Electronic Engineering (5 years)


Required experience:

  • more than 7 years in the sector of the design and/or the verification and/or the analysis of digital architectures
  • knowledge of the digital architectures of System on Chip based on programmable cores


Desired experience:

  • experience in the FMEDA analysis.
  • experience on RISK multicore architectures based on ARM and MIPS and on its programming.
  • Knowledge of the base cases in the automotive and industrial environment of the Functional Safety.


Main tasks:

  • FMEDA analysis of complex SoC based on programmable cores.
  • Specifications definition for the products development: HW IP and firmware for Functional Safety applications.
  • Management of RTL simulations and gate level of complex Systems on Chip for fault injection based on the Synopysis toolchain (work team composed of 4-5 members)
  • Management of the relationships with the customers.


Availability:
Immediate, but the integration during the 2017 is took into consideration


Location:
Pontedera.


Business trips:
Possibility of national and internation business trips for meetings with the customers (on the average, no more than one business trip per month).